RISC-V Assembly Resources

CS 3410 uses the 64-bit RISC-V (pronounced risk-five) instruction set architecture (ISA). RISC-V is a modern reduced instruction set computer (RISC) architecture. RISC-V is unique because it’s an open instruction set that anyone can implement without any kind of licensing. (That’s in contrast to the two most popular ISAs, Arm and x86, which both require expensive licenses to implement in hardware.)

Here are some references you might find helpful when writing and reading RISC-V assembly code.

Reference Materials

• Use a shorter reference card:
  • MIT’s RISC-V reference card is a compact reference for all of the instructions in the 32-bit ISA. But remember that, in 3410, we use the 64-bit version of the ISA, so there are some missing instructions and some subtly differing semantics.
  • This exhaustive reference sheet contains instructions for the 32-bit version, 64-bit version, and beyond.
• For the definitive description of what every instruction does and how it’s encoded, see the official ISA manual. It’s long, though, and can get a little bit technical.

Online Tools

• Cornell’s new experimental RISC-V interpreter supports 64-bit RISC-V, and replaces the previous 32-bit interpreter. Note that the old interpreter, which is now deprecated, was designed for the 32-bit ISA, while the new version more closely aligns with the 64-bit ISA taught in class.
• Venus is a powerful interactive RISC-V simulator. It is more complicated to use, but it supports more RISC-V instructions.