Research Topics
Power Management and Thread Scheduling for Unpredictably Heterogeneous CMP Architectures
As Moore's Law continues to deliver exponentially more transistors on a die over time, computer architects have begun to design chip multiprocessors (CMPs) whereby these transistors are used to create additional cores on the same chip. As silicon feature sizes decrease in every subsequent technology generation, the manufacturing process has become less reliable. Furthermore, the microscopic transistors and wires on these chips have become more susceptible to wear-out related errors. As these hard errors and variations become more prevalent, manufacturers will not be able to afford to discard affected chips, but will instead be forced to develop microprocessors that tolerate these shortcomings. Since the errors and variations are a result of largely random physical processes that occur during manufacturing and usage, each core on a CMP will be uniquely affected. The resulting chip will be an unpredictably heterogeneous CMP, even though it may have been designed as a homogeneous architecture. Many workloads will consist of a number of applications running simultaneously across the cores of the CMP. Each application will exhibit different program characteristics and will also demonstrate phase behavior during execution.
My research seeks to maximize performance and power-efficiency by leveraging the heterogeneity among the processor cores and application workload. I have explored a number of directions in this domain. My first project focuses on a matching problem that involves finding the best assignment of threads to cores on the CMP. We solve this matching problem by implementing schedulers based an optimization algorithm called Hungarian Algorithm, as well as artificial intelligence search techniques. Other work examines the scalability limits of these algorithms to future microprocessors with tens or hundreds of cores. I have also studied algorithms for combining multi-core global power optimization with thread scheduling. I am current working on developing highly scalable algorithm which will tackle power management and scheduling in tandem with low computational complexity.
Dynamic Thermal Management in Clustered SMT Microarchitectures
Clustered microarchitectures are microprocessor designs where the back end resources of the pipeline, including the instruction issue queues, register files, execution units, and write-back circuitry, are partitioned into multiple separate groups. This has the key benefits of reducing design complexity and dynamic power dissipation. In order to facilitate inter-cluster communication, changes must be made to the rename stage to track inter-cluster dependencies and a mechanism must be added to pass source registers between clusters. In order to reduce the cost of this communication, a steering mechanism is integrated into the dispatch pipeline stage which tries to send instructions to the same cluster as register values they depend upon.
In this work, I investigated a simultaneous multi-threaded (SMT) clustered microarchitecture. Differences between the program and phase behavior of the multiple threads lead to spatial and temporal temperature variations among the back end clusters. I developed intelligent steering algorithms which exploit these variations to provide low cost dynamic thermal management (DTM) which was competitive with prior state-of-the-art DTM techniques based on dynamic voltage and frequency scaling (DVFS). My DTM method has the advantage of not requiring per-core DVFS which may be costly and difficult to implement in future CMPs with low supply voltages and many cores.
Research Positions
Research Assistant for Professor David Albonesi from May 2005 to August 2008 and January 2009 to present.
Research Assistant for Professor Keshav Pingali from August 2004 to December 2004.
General Research Interests
The application of artificial intelligence, computer science theory, operations research, and optimization to computer architecture and other areas such as finance; multi-threaded, multi-core, and multi-processor designs; power, thermal, and reliability issues in computer architecture; and complexity-effective microprocessor design.