Week | Day | Date | Topic | Reading | Lab | Release | Deadline | Comments | |
---|---|---|---|---|---|---|---|---|---|
1 | Thu | Jan 25 | Administrivia
[ Introduction [ ] |
]
Chapter 1 (1.1-1.3) | Lab 0: Git/UNIX | No office hours this week; Tuesday Labs can be made up on Thursday/Friday morning | |||
2 | Tue | Jan 30 | Gates & Logic [ | ]Sections 2.1-2.6 | Lab 1: Intro to Logisim |
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Thu | Feb 1 | Numbers & Arithmetic [ | ]Chapter 3 (3.1-3.8) | ||||||
3 | Tue | Feb 6 | State
[ Memory [ ] FSMs [ ] |
]Sections 4.1-4.4 | Lab 2: LeftShift32 |
P1: ALU | |||
Thu | Feb 8 | Sections 7.1-7.8 | |||||||
4 | Tue | Feb 13 | Intro to a MIPS Processor [ | ]Sections 5.1-5.5 | Lab 3: CPU Basics | ||||
Thu | Feb 15 | Ch 5.6-5.11 | |||||||
Fri | Feb 16 | P1 due @ 11:59PM | |||||||
Tue | Feb 20 | February Break, No Class | Lab 4: Circuit Minimization |
P2: MiniMIPS | |||||
Thu | Feb 22 | Pipelining [ | ]Sections 6.1-6.3 | ||||||
5 | Tue | Feb 27 | Pipelining w/Data Hazards | Sections 2.7-2.14 | Lab 5: Pipelining |
C Homework 1 due @ 11:59 PM | (b/c Ch. 2 is AWFULly large) | ||
Wed | Feb 28 | P2 Design Doc due @ 11:59PM | |||||||
Thu | Mar 1 | Pipelining w/Control Hazards | Sections 6.4-6.5 | ||||||
6 | Tue | Mar 6 | Calling Conventions [ | ]Chapter 10 (10.1-10.3) | Lab 6: Finite State Machines |
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Thu | Mar 8 | ||||||||
7 | Tue | Mar 13 | Performance [ | ]Chapter 8 (8.1-8.2) | Lab 7: Calling Conventions |
P3:Fully-Pipelined MIPS | P2 due @ 11:59PM | ||
Thu | Mar 15 | RISC, CISC, and ISA Variations [ | ]Chapter 9 (9.1-9.6) | PRELIM 1 @ 7:30 B14 Hollister Hall, 245 Olin Hall, 255 Olin Hall. 4:45pm is an alternative if 7:30pm is a conflict with a larger class. | |||||
8 | Mon | Mar 19 | |||||||
Tue | Mar 20 | Linkers & Loaders [ | ]Chapter 11 (11.1-11.4) | Lab 8: Selection Sort |
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Thu | Mar 22 | Caches [ | ]Sections 12.1-12.5 | P3 WIP Circuit due @ 11:59PM | |||||
Sun | Mar 26 | ||||||||
9 | Tue | Mar 27 | Lab 9: GDB |
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Thu | Mar 29 | Sections 12.6-12.7 | P3 due @ 11:59PM | ||||||
Tue | Apr 3 | Spring Break, No Class | |||||||
Thu | Apr 5 | Spring Break, No Class | |||||||
10 | Tue | Apr 10 | Virtual Memory [ | ]Sections 13.1.1-13.1.4 | Lab 10: Arraylist |
P4:Buffer Overflow | |||
Thu | Apr 12 | Sections 13.1.5-13.1.11 | |||||||
11 | Tue | Apr 17 | Exceptional Control Flow [ | ]Section 14.1 - 14.2 | Lab 11: Caches and Virtual Memory |
P5: Cache Collusion | |||
Wed | Apr 18 | P4 due @ 11:59PM | |||||||
Thu | Apr 19 | Multicore [ | ]Sections 15.1-15.5 | ||||||
12 | Tue | Apr 24 | Sections 15.6-15.9 | Lab 12: First 5 Malloc Tests | C Homework 2 due on Apr 23th @ 11:59 PM | ||||
Thu | Apr 26 | ||||||||
Fri | Apr 27 | P5 due @ 11:59PM | |||||||
13 | Tue | May 1 | I/O [ | ]Chapter 16 (16.1) | Optional Lab: Practice Prelims | P6: Malloc | |||
Thu | May 3 | Storage [ | ]Chapter 17 (17.1 - 17.2) | PRELIM 2 @ 7:30 185 Statler Hall. 4:45pm is an alternative if 7:30pm is a conflict with a larger class. | |||||
14 | Mon | May 7 | P5 Cache Collusion Tournament 5-7pm at Kimball B11 | ||||||
Tue | May 8 | Conclusions | [ | ]No Labs This Week | |||||
Wed | May 9 | P6 Design Doc due @ 11:59 PM | |||||||
15 | Tues | May 15 | P6 due @ 4:30 PM |