Department of Computer Science
COLLOQUIUM

Thursday, December 2, 2004
4:15pm
B17 Upson Hall

David Albonesi
Cornell, Electrical & Computer Engineering

Nanoscale CMOS Microprocessors:
Challenges and Directions

The continuing advancement of Moore's Law has brought great benefits to the microprocessor industry, but in the years ahead, there are a number of daunting challenges to be faced. Left unchecked, power dissipation will prevent future microprocessor performance improvements. We are already at the point where development efforts are being curtailed due to excessive heat, and the problem is slated to grow worse in the future. To make matters worse, further scaling of CMOS technology will lead to higher defect levels, a growing vulnerability to soft errors, and issues of long term chip wear-out.

The usual solutions to these problems, reconfigurability and redundancy, are very power inefficient. The reality is that we don't yet know how we are going to deliver reliable, high performance microprocessors, within cost and power constraints, ten years down the road.

These challenges create a very exciting time to be a processor microarchitect. Microprocessors will need to be exceedingly efficient in running a variety of systems and application software, while detecting, and gracefully handling, hard and soft errors. This talk will describe a direction for future microprocessors in which highly partitioned, adaptive, and reusable hardware building blocks are cooperatively managed by hardware and software. A key theme is the adaptation of this flexible hardware fabric to environmental conditions, application characteristics including criticality, and runtime hardware events such as errors and potential thermal overloads. Some preliminary results in using this approach to improve performance and power efficiency are presented.